A simple smart time-to-digital convertor based on vernier method for a high resolution LYSO MicroPET
暂无分享,去创建一个
Rong Zhou | Tianyu Ma | Yaqiang Liu | Shi Wang | Xiaowen Kang | Zhaoxia Wu | Yongjie Jin | Xisan Sun
[1] I. Peric,et al. Multi-Channel Readout ASIC for ToF-PET , 2006, 2006 IEEE Nuclear Science Symposium Conference Record.
[2] Luca Fanucci,et al. On the differential nonlinearity of time-to-digital converters based on delay-locked-loop delay lines , 2001 .
[3] G. C. Moyer,et al. Precise delay generation using the Vernier technique , 1996 .
[4] D. M. Santos,et al. A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip , 1995, 1995 IEEE Nuclear Science Symposium and Medical Imaging Conference Record.
[5] A. Marchioro,et al. A flexible multi-channel high-resolution time-to-digital converter ASIC , 2000, 2000 IEEE Nuclear Science Symposium. Conference Record (Cat. No.00CH37149).
[6] Poras T. Balsara,et al. A wide-range, high-resolution, compact, CMOS time to digital converter , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[7] Józef Kalisz,et al. Review of methods for time interval measurements with picosecond resolution , 2004 .
[8] Jian Song,et al. A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays , 2006, IEEE Transactions on Nuclear Science.
[9] J. J. Williams,et al. High-precision TDC in an FPGA using a 192 MHz quadrature clock , 2002, 2002 IEEE Nuclear Science Symposium Conference Record.
[10] G. Bertschinger,et al. MWPC-readout with the N110 TDC under Linux using a flexible, low-cost FPGA solution , 2005, IEEE Nuclear Science Symposium Conference Record, 2005.
[11] T. Rahkonen,et al. ECL and CMOS ASICs for time-to-digital conversion , 1989, Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,.
[12] J. M. Rochelle,et al. Performance characteristics of a new generation of processing circuits for PET applications , 2002, 2002 IEEE Nuclear Science Symposium Conference Record.
[13] A. Marchioro,et al. An integrated 16-channel CMOS time to digital converter , 1994 .
[14] Chun-Chi Chen,et al. A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy , 2007, IEEE Transactions on Nuclear Science.
[15] Jinyuan Wu,et al. Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA) , 2003, 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515).
[16] Chun-Chi Chen,et al. A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[17] S.S. Junnarkar,et al. An FPGA-based, 12-channel TDC and digital signal processing module for the RatCAP scanner , 2005, IEEE Nuclear Science Symposium Conference Record, 2005.
[18] M. Mota,et al. A high-resolution time interpolator based on a delay locked loop and an RC delay line , 1999, IEEE J. Solid State Circuits.
[19] Peter J. Kindlmann,et al. Phase Stabilized Vernier Chronotron , 1966 .
[20] E. Hazen,et al. A new multihit digital TDC implemented in a gallium arsenide ASIC , 1994 .
[21] P. Dudek,et al. A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.
[22] J. Kalisz,et al. Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution , 1997 .
[23] Xiaohui Li,et al. High-Resolution and Multi-Channel Time Interval Counter Using Time-to-Digital Converter and FPGA , 2007, 2007 IEEE International Frequency Control Symposium Joint with the 21st European Frequency and Time Forum.
[24] Gordon Russell,et al. A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).
[25] G. Kemmerling,et al. Development of a High Resolution TDC Module for the WASA Detector System Based on the GPX ASIC , 2006, 2006 IEEE Nuclear Science Symposium Conference Record.
[26] P. Wilson,et al. A new time-to-digital converter for the central tracker of the colliding detector at Fermilab , 2004, IEEE Symposium Conference Record Nuclear Science 2004..
[27] J. M. Rochelle,et al. A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications , 2004, IEEE Journal of Solid-State Circuits.
[28] Mounir Boukadoum,et al. On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs , 2007, 2007 IEEE International Symposium on Circuits and Systems.