Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques

In VLSI CMOS circuit design chip area, signal propagation delay and power dissipation are conflicting criteria that need to be optimized in order to improve performance. Full circuit simulation and manual optimization can be costly and time consuming. We present here a method of obtaining different circuit configurations from a given multiple-output Boolean expression. An optimum circuit is selected from the solution space using a multiple attribute decision making (MADM) technique.<<ETX>>

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