A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

Reliability is a significant strategy concern for modern day multi core embedded systems. On chip communicating systems are vulnerable to permanent network faults and transient faults which might essentially affect the performance of the system. Targeting at fault tolerance solution for cores with faults in Network on Chip (NoC), this paper proposes an energy efficient fault tolerant NoC architecture using spare core. The proposed strategy comprises of finding smallest rectangular region to place the given application using a heuristic technique, and mapping vertices within the selected region, and selecting a region which results maximum overall performance and minimum communication energy. Spare core is placed within a region and connected to the vertices. Many application core graphs are used to evaluate the proposed technique. The simulation outcomes of many fault injection tests indicate that the proposed technique results in performance enhancement while also saving communication energy.

[1]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[2]  Pasi Liljeberg,et al.  Fault Tolerance Analysis of NoC Architectures , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[3]  Chita R. Das,et al.  Exploring Fault-Tolerant Network-on-Chip Architectures , 2006, International Conference on Dependable Systems and Networks (DSN'06).

[4]  Hamid R. Zarandi,et al.  A fault-tolerant core mapping technique in networks-on-chip , 2013, IET Comput. Digit. Tech..

[5]  Mariagiovanna Sami,et al.  Design of Fault Tolerant Network Interfaces for NoCs , 2011, 2011 14th Euromicro Conference on Digital System Design.

[6]  Ahmed Louri,et al.  Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[8]  Sandip Kundu,et al.  Task model for on-chip communication infrastructure design for multicore systems , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[9]  Radu Marculescu,et al.  FARM: Fault-aware resource management in NoC-based multiprocessor platforms , 2011, 2011 Design, Automation & Test in Europe.

[10]  David Z. Pan,et al.  A3MAP: architecture-aware analytic mapping for networks-on-chip , 2010, ASP-DAC 2010.

[11]  Jizhou Sun,et al.  An Efficient Topology Reconfiguration Algorithm for NoC Based Multiprocessor Arrays , 2013, 2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing.

[12]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[13]  M. H. Vasantha,et al.  Communication energy constrained spare core on NoC , 2015, 2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT).

[14]  Chita R. Das,et al.  A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[15]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[16]  Cristinel Ababei,et al.  Achieving network on chip fault tolerance by adaptive remapping , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[17]  Onur Derin,et al.  Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[18]  Bo Yang.  Towards Optimal Application Mapping for Energy-Efficient Many-Core Platforms , 2013 .

[19]  Y. B. Nithin Kumar,et al.  A fine grained position for modular core on NoC , 2015, 2015 International Conference on Computer, Communication and Control (IC4).

[20]  David Z. Pan,et al.  A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[21]  Santanu Chattopadhyay,et al.  Energy and performance evaluation of a dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip architecture , 2010, 2010 Annual IEEE India Conference (INDICON).

[22]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[23]  Avinash Karanth Kodi,et al.  Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).