Ultra Low Power 1-Bit Full Adder

In this paper we propose a new 9 transistor 1-bit full adder. The proposed circuit performs efficiently in subthreshold region to employ in ultra low power applications. The main design objective for this new circuit is low power consumption and full voltage swing at a low supply voltage. The proposed cell also remarkably improves the power consumption, power delay product and has better noise immunity when compared to the existing deigns. All simulations are performed on 45nm standard models on Tanned EDA tool version 12.6.

[1]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[2]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[3]  Yintang Yang,et al.  Novel low power full adder cells in 180nm CMOS technology , 2009, 2009 4th IEEE Conference on Industrial Electronics and Applications.

[4]  Tripti Sharma,et al.  High performance full adder cell: A comparative analysis , 2010, 2010 IEEE Students Technology Symposium (TechSym).

[5]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[6]  Tripti Sharma,et al.  A novel CMOS 1-bit 8T full adder cell , 2010 .

[7]  M.Hosseinghadiry,et al.  Two New Low Power High Performance Full Adders with Minimum Gates , 2009 .

[8]  Z. Abid,et al.  New parallel multipliers based on low power adders , 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

[9]  Tripti Sharma,et al.  High speed, low power 8t full adder cell with 45% improvement in threshold loss problem , 2010, ICN 2010.

[10]  CMOS micromachined structures using transistors in the subthreshold region for thermal sensing , 2006 .

[11]  M.B. Srinivas,et al.  New improved 1-bit full adder cells , 2008, 2008 Canadian Conference on Electrical and Computer Engineering.

[12]  Anantha Chandrakasan,et al.  Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.

[13]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .

[14]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[15]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[16]  Shubhajit Roy Chowdhury,et al.  A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates , 2008 .

[17]  Walid S. Saba,et al.  ANALYSIS AND DESIGN , 2000 .

[18]  Po-Ming Lee,et al.  Novel 10-T full adders realized by GDI structure , 2007, 2007 International Symposium on Integrated Circuits.

[19]  Yannis Tsividis,et al.  Mixed analog-digital VLSI devices and technology , 1996 .