A Leakage-Tolerant 16 – Bit Comparator using Lector Technique Based Footless Domino Logic Circuit

The continuous scaling has resulted in increased sub-threshold leakage current due to decreased threshold voltage. LECTOR is a technique to decrease the problem of leakage in CMOS circuits, it includes a p-type and n-type leakage controlled transistors (LCTs), which are self-controlled, between supply to ground which offers the extra resistance which will reduce the problem of leakage current in the CMOS circuits. In this paper 16-bit Lector based standard foot-less domino (SFLD) comparator is introduced, which provides 74% efficient reduction in leakage and is also efficient in terms of performance compared to basic 16-bit SFLD comparator. Simulations are performed in gpdk_90 nm CMOS technology using cadence virtuoso tool.

[1]  Zhiyu Liu,et al.  Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Gürhan Küçük,et al.  A circuit-level implementation of fast, energy-efficient CMOS comparators for high-performance microprocessors , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  H. Iwai,et al.  1.5 nm direct-tunneling gate oxide Si MOSFET's , 1996 .

[4]  Mark C. Johnson,et al.  Leakage control with efficient use of transistor stacks in single threshold CMOS , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[5]  K. Roy,et al.  A leakage-tolerant high fan-in dynamic circuit design style [logic circuits] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[6]  Abhijeet Dutta,et al.  Performance comparison of 3 bit ECRL ADC with conventional logic style , 2016, 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT).

[7]  Sunil P. Khatri,et al.  CMOS Comparators for High-Speed and Low-Power Applications , 2006, 2006 International Conference on Computer Design.

[8]  Eby G. Friedman,et al.  Domino logic with variable threshold voltage keeper , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Preetisudha Meher,et al.  Modifications in CMOS Dynamic Logic Style: A Review Paper , 2015 .

[10]  Kaushik Roy,et al.  Leakage control for deep-submicron circuits , 2003, SPIE Microtechnologies.