Optical lithography simulation using wavelet transform

Optical Lithography is an indispensible step in the process flow of Design for Manufacturability (DFM). Optical lithography simulation is a compute intensive task and simulation performance, or lack thereof can be a determining factor in time to market. Thus, the efficiency of lithography simulation is of paramount importance. Coherent decomposition is a popular simulation technique for aerial imaging simulation. In this paper, we propose an approximate simulation technique based on the 2D wavelet transform and use a number of optimization methods to further improve polygon edge detection. Results show that the proposed method suffers from an average error of less than 5% when compared with the coherent decomposition method. The benefits of the proposed method are (i) >10X increase in performance and more importantly (ii) it allows very large circuits to be simulated while some commercial tools are severely capacity limited. Approximate simulation is quite attractive for layout optimization where it may be used in a loop and may even be acceptable for final layout verification.

[1]  David Z. Pan,et al.  A novel intensity based optical proximity correction algorithm with speedup in lithography simulation , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[2]  James A. Culp,et al.  Process window OPC for reduced process variability and enhanced yield , 2006, SPIE Advanced Lithography.

[3]  David Z. Pan,et al.  RADAR: RET-aware detailed routing using fast lithography simulations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  Roy D. Wallen,et al.  The Illustrated Wavelet Transform Handbook , 2004 .

[5]  Peng Yu,et al.  Fast Lithography Image Simulation By Exploiting Symmetries in Lithography Systems , 2008, IEEE Transactions on Semiconductor Manufacturing.

[6]  Andrew B. Kahng,et al.  Subwavelength optical lithography: challenges and impact on physical design , 1999, ISPD '99.

[7]  Jason Cong,et al.  Lithographic aerial image simulation with FPGA-based hardwareacceleration , 2008, FPGA '08.

[8]  Peng Yu,et al.  ELIAS: An Accurate and Extensible Lithography Aerial Image Simulator With Improved Numerical Algorithms , 2009, IEEE Transactions on Semiconductor Manufacturing.

[9]  K. Stetson,et al.  Progress in optics , 1980, IEEE Journal of Quantum Electronics.

[10]  Yuri Granik,et al.  OPC methods to improve image slope and process window , 2003, SPIE Advanced Lithography.

[11]  Paul S. Addison,et al.  The Illustrated Wavelet Transform Handbook , 2002 .

[12]  Michael S. Yeung,et al.  Fast and rigorous three-dimensional mask diffraction simulation using Battle-Lemarie wavelet-based multiresolution time-domain method , 2003, SPIE Advanced Lithography.

[13]  Qi-De Qian,et al.  Controlling defocus impact on OPC performance , 2003, Photomask Japan.

[14]  Lars Liebmann,et al.  Layout impact of resolution enhancement techniques: impediment or opportunity? , 2003, ISPD '03.

[15]  Thomas Kailath,et al.  Phase-shifting masks for microlithography: automated design and mask requirements , 1994 .

[16]  Tsann-Bim Chiou,et al.  Development of layout split algorithms and printability evaluation for double patterning technology , 2008, SPIE Advanced Lithography.

[17]  Sunyoung Koo,et al.  Issues and challenges of double patterning lithography in DRAM , 2007, SPIE Advanced Lithography.

[18]  Vincent Wiaux,et al.  Double patterning design split implementation and validation for the 32nm node , 2007, SPIE Advanced Lithography.

[19]  Yu Cao,et al.  Optimized hardware and software for fast full-chip simulation , 2004, SPIE Advanced Lithography.

[20]  David Z. Pan,et al.  Fast lithography simulation under focus variations for OPC and layout optimizations , 2006, SPIE Advanced Lithography.

[21]  Andrew B. Kahng,et al.  Layout decomposition for double patterning lithography , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[22]  Andrew B. Kahng,et al.  Revisiting the layout decomposition problem for double patterning lithography , 2008, Photomask Technology.

[23]  Vincent Wiaux,et al.  Double pattern EDA solutions for 32nm HP and beyond , 2007, SPIE Advanced Lithography.

[24]  Avideh Zakhor,et al.  Fast optical and process proximity correction algorithms for integrated circuit manufacturing , 1998 .

[25]  Vincent Wiaux,et al.  Split and design guidelines for double patterning , 2008, SPIE Advanced Lithography.

[26]  David Z. Pan,et al.  Process variation aware OPC with variational lithography modeling , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[27]  Y. Granik,et al.  Considerations for the use of defocus models for OPC , 2005, SPIE Advanced Lithography.

[28]  David Z. Pan,et al.  True process variation aware optical proximity correction with variational lithography modeling and model calibration , 2007 .

[29]  C. Mack Fundamental principles of optical lithography , 2007 .

[30]  Roger Fabian W. Pease,et al.  Exploiting structure in fast aerial image computation for integrated circuit patterns , 1997 .

[31]  Kun Yuan,et al.  Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Kun Yuan,et al.  Layout Decomposition for Triple Patterning Lithography , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.