Automatic Generation of Communication Architectures

In this paper, we propose automatic generation of bus-based communication architectures from an abstract model reflecting only the communication topology. Tasks include protocol selection for each bus, master/slave assignment for each component, interrupt handling and addressing for synchronization between components, and arbitration to resolve multiple accesses on a bus. We present a set of experimental results demonstrating how the proposed approach works on typical system designs. Experimental results show the benefits of our methodology and demonstrate the effectiveness of automatic model generation for communication design.

[1]  Daniel Gajski,et al.  Automatic communication refinement for system level design , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[2]  Jan Madsen,et al.  Integrating communication protocol selection with partitioning in hardware/software codesign , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

[3]  Guy Gogniat,et al.  Communication synthesis and HW/SW integration for embedded system design , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[4]  Daniel D. Gajski,et al.  Communication Link Synthesis for SoC , 2004 .

[5]  Miltos D. Grammatikakis,et al.  IPSIM: systemc 3.0 enhancements for communication refinement , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Wayne H. Wolf,et al.  Communication synthesis for distributed embedded systems , 1995, ICCAD.

[7]  Diederik Verkest,et al.  Hardware/software co-design of digital telecommunication systems , 1997, Proc. IEEE.

[8]  Gabriela Nicolescu,et al.  Component-based design approach for multicore SoCs , 2002, DAC '02.

[9]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[10]  Miltos D. Grammatikakis,et al.  IPSIM: SystemC 3.0 enhancements for communication refinement [SoC design] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[11]  A. Gerstlauer,et al.  System-level communication modeling for network-on-chip synthesis , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..