TSV-Aware 3 D Physical Design Tool Needs for Faster Mainstream Acceptance of 3 D ICs

This article presents several grand challenges in the area of physical design for through-silicon via (TSV) based 3D ICs. Most of these issues are centered around TSVs, which are a new element of the 3D IC layout. Fundamental understanding of the electrical, mechanical, and thermal properties of TSVs is essential in successful physical design of TSV-based 3D ICs. Further investigation of the impact of TSVs on the overall layout qualities such as performance, power, reliability, and manufacturability is crucial. As of early 2010, there is no commercial tool available for automatic placement and routing and sign-off analysis of timing, power, reliability, and manufacturability for TSV-based layouts. This calls for a concerted effort in developing such tools, which will have significant impact on the mainstream acceptance of TSV-based 3D IC technologies and products.

[1]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[2]  Sung Kyu Lim,et al.  Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[3]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[4]  Paul S. Andry,et al.  Fabrication and characterization of robust through-silicon vias for silicon-carrier applications , 2008, IBM J. Res. Dev..

[5]  Lei Jiang,et al.  Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[6]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[7]  Sung Kyu Lim,et al.  A study of stacking limit and scaling in 3D ICs: an interconnect perspective , 2009, 2009 59th Electronic Components and Technology Conference.

[8]  Hsien-Hsin S. Lee,et al.  Pre-bond testable low-power clock tree design for 3D stacked ICs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[9]  Sung Kyu Lim,et al.  Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs , 2009, SLIP '09.