Ultralow Power Processor Design with 3D IC Operating at Sub/Near-Threshold Voltages

The requirement for ultra low power and energy efficient systems is becoming more and more important with increase in the use of miniaturized portable devices and unsupervised remote sensor systems. Three-dimensional integration is an emerging technology which helps in reducing footprint as well as power. In this work, we carry out a detailed study of the combined benefits of 3D ICs and low-voltage supply designs to obtain maximum energy efficiency. We implement different types of circuits in conventional 2D and TSV-based 3D designs at different supply voltages varying from nominal to subthreshold voltages. The impact of 3D integration on these different types of circuits is analyzed. Our study is based on power and energy comparison of full GDSII layouts. Our study confirms that sub/near-threshold circuits indeed offer a few orders of magnitude power versus performance trade-off with further improvement due to 3D implementation. In addition, 3D designs reduce the footprint area up to 78 % and wire length up to 33 % compared with the 2D counterpart. Our studies also show that thermal and IR-drop issues are negligible in subthreshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low-power and high-memory bandwidth advantages of many-core 3D subthreshold circuits.

[1]  J. Shott,et al.  A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[2]  Mario Konijnenburg,et al.  Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[4]  Jun Zhou,et al.  A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Jason Cong,et al.  Edge separability-based circuit clustering with application to multilevel circuit partitioning , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Hsien-Hsin S. Lee,et al.  3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[8]  Mark Anders,et al.  Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.

[9]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[10]  Hong Wang,et al.  How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[11]  David Blaauw,et al.  Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores , 2012, 2012 IEEE International Solid-State Circuits Conference.

[12]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[13]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[14]  Daeyeon Kim,et al.  A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode , 2009, IEEE Journal of Solid-State Circuits.

[15]  David Blaauw,et al.  Ultralow-voltage, minimum-energy CMOS , 2006, IBM J. Res. Dev..