Optimization of transistors for very high frequency dc-dc converters

This document presents a method to optimize integrated LDMOS transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout vs. loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50 MHz converter, resulting in a 35% reduction in power loss over an un-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 20-V design rules is validated at 35-V, offering reduced parasitic resistance and capacitance. Compared to the original design, loss is up to 75% lower in the example application.

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