A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs

A metastability-immune error-resilient flip-flop (MIERFF) is proposed to eliminate timing margins. It detects timing errors by generating and capturing a pulse that is wide enough to avoid metastability, in response to the data input transition. Timing errors are immediately corrected by dynamically making the master latch transparent to resample the late-arriving data. The MIERFF improves the system reliability and reduces the correction performance penalty. We apply the MIERFF to a 32-bit embedded processor in a 40 nm CMOS technology. Simulation results show that the proposed design under 0.6V consumes 47% less energy than the traditional worst case design and achieves 6%–38% energy benefits over previous error detection and correction designs.

[1]  Ali Afzali-Kusha,et al.  Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  David Blaauw,et al.  Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction , 2013, IEEE Journal of Solid-State Circuits.

[3]  Robert C. Aitken,et al.  Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience , 2014, IEEE Transactions on Computers.

[4]  Dennis Sylvester,et al.  Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails , 2014, IEEE Journal of Solid-State Circuits.

[5]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[6]  Yiorgos Tsiatouhas,et al.  Timing Error Tolerance in Small Core Designs for SoC Applications , 2016, IEEE Transactions on Computers.

[7]  Yiorgos Tsiatouhas,et al.  Cost and power efficient timing error tolerance in flip-flop based microprocessor cores , 2012, 2012 17th IEEE European Test Symposium (ETS).

[8]  Bishnu Prasad Das,et al.  A metastability immune timing error masking flip-flop for dynamic variation tolerance , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

[9]  Youhua Shi,et al.  Timing monitoring paths selection for wide voltage IC , 2016, IEICE Electron. Express.

[10]  Mingoo Seok,et al.  Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique , 2015, IEEE Journal of Solid-State Circuits.

[11]  I-Chyn Wey,et al.  Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications , 2015, IEICE Electron. Express.

[12]  Trevor Mudge,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, VLSIC 2005.

[13]  K.A. Bowman,et al.  Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.