Fence-aware detailed-routability driven placement

We present a detailed-routability driven placement algorithm with fence constraint. It is two-step process involving global placement and detailed placement. Our global placement is an upper-bound-lower-bound optimization framework honoring fence constraint. The lower-bound step is a wirelength-driven analytical placement solved by a box-constrained conjugate gradient (CG) method. The upper-bound step is a fence-by-fence rough legalization to reduce cell overlap, routing congestion, while satisfying fence constraint. In detailed placement, we improve the wirelength with design-rule-aware local cell movement. Congestion-guided bin-based target density control is used to further enhance circuit routability during the movement process. By comparing the results to the participating teams of the 2015 ISPD Placement Contest [1], our placer shows competitive results in terms of wirelength, routability, and design rule satisfaction.

[1]  Andrew A. Kennings,et al.  Detailed placement accounting for technology constraints , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[2]  Ulf Schlichtmann,et al.  Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Dongjin Lee,et al.  SimPL: An Effective Placement Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Chung-Kuan Cheng,et al.  ePlace: Electrostatics based placement using Nesterov's method , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Jarrod A. Roy,et al.  What makes a design difficult to route , 2010, ISPD '10.

[6]  Tao Huang,et al.  Ripple 2.0: High quality routability-driven placement via global router integration , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Yao-Wen Chang,et al.  Routability-driven analytical placement for mixed-size circuit designs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Yih-Lang Li,et al.  Multi-threaded collision-aware global routing with bounded-length maze routing , 2010, Design Automation Conference.

[9]  Alberto Sangiovanni-Vincentelli,et al.  TimberWolf3.2: A New Standard Cell Placement and Global Routing Package , 1986, DAC 1986.

[10]  D. Chinnery,et al.  ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement , 2015, ISPD.

[11]  Yao-Wen Chang,et al.  Routability-driven placement for hierarchical mixed-size circuit designs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  Yao-Wen Chang,et al.  Detailed-Routing-Driven analytical standard-cell placement , 2015, The 20th Asia and South Pacific Design Automation Conference.

[13]  David T. Westwick,et al.  High performance global placement and legalization accounting for fence regions , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[14]  Andrew B. Kahng,et al.  Optimal partitioners and end-case placers for standard-cell layout , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Cheng-Kok Koh,et al.  Case study for placement solutions in ispd11 and dac12 routability-driven placement contests , 2013, ISPD '13.

[16]  Sachin S. Sapatnekar,et al.  GLARE: Global and local wiring aware routability evaluation , 2012, DAC Design Automation Conference 2012.

[17]  Hung-Ming Chen,et al.  Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability , 2015, ISPD.

[18]  Chris C. N. Chu,et al.  Pin Accessibility-Driven Detailed Placement Refinement , 2017, ISPD.

[19]  Jin Hu,et al.  A SimPLR method for routability-driven placement , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[20]  Andrew B. Kahng,et al.  Scalable detailed placement legalization for complex sub-14nm constraints , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Jin Hu,et al.  Taming the complexity of coordinated place and route , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[22]  Evangeline F. Y. Young,et al.  Cell density-driven detailed placement with displacement constraint , 2014, ISPD '14.

[23]  Tao Lin,et al.  POLAR 2.0: An effective routability-driven placer , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).