Modified Nodal Analysis(MNA) is a generalized method of discrete linear circuit analysis as a matrix equation, in which the matrix order is the sum of the number of nodes and the number of voltage sources, it also have additional lines for dynamic elements, such as capacitors and inductors, but for this work these lines were kept implicit using Nodal Analysis’ equations for historic sources. As this order grows, the computational effort for solving the equation grows to the square of its size. Therefore, optimizations are in place to better utilize the processing power of a hardware, so that more complex circuits can fit in less powerful simulators, avoiding problems associated with high values of time step, such as mathematical inaccuracy and instability. This paper presents a boost converter and a PI controller, each implemented in a separate Texas Instruments’ F28377S, assembled in a Hardware in the Loop configuration. The MNA is used for the plant discretization and a matrix multiplier is developed to solve it. This multiplier is then optimized with two methods: sparse matrix handling and a parallel multiplier. The sparsity is dealt with by storing the matrix in a Compressed Sparse Row(CSR) format and adjusting the multiplier. The parallel matrix multiplier is implemented using both the Control Law Accelerator(CLA) and the main CPU to reduce the processing time. The results presented by the comparison of each program shows that the The results are drawn from each multiplier and comparison is made between them, leading to a conclusion of the benefits of such implementation.
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