Combinational logic devices lack true memory, and, therefore, lack the ability to perform sequential operations. Yet their presence in a sequential machine may be indispensable. This chapter defines that sequential machines, or simply state machines, possess true memory and can issue time-dependent sequences of logic signals controlled by present and past input information. These sequential machines may also be synchronous because the data path is controlled by a system clock. In synchronous sequential machines, input data are introduced into the machine and are processed sequentially according to some algorithm, and outputs are generated—all regulated by a system clock. The chapter also highlights the synchronous sequential machines and their design, analysis, and operation. A sequential machine always has a finite number of states and is therefore called a finite state machine (FSM) or simply a state machine. Thus, if there are N state variables, there can be no more than 2 N states in the FSM and no fewer than 2.
[1]
Donald Leo Dietmeyer,et al.
Logic design of digital systems
,
1971
.
[2]
Alan W. Shaw.
Logic Circuit Design
,
1993
.
[3]
J. David Irwin,et al.
Digital Logic Circuit Analysis and Design
,
1995
.
[4]
Beth V. Yarbrough.
Digital Logic: Applications and Design
,
1996
.
[5]
Richard F. Tinder.
Digital Engineering Design: A Modern Approach
,
1991
.
[6]
John F. Wakerly,et al.
Digital design - principles and practices
,
1990,
Prentice Hall Series in computer engineering.
[7]
David J. Comer.
Digital logic and state machine design
,
1984
.
[8]
Herbert Taub,et al.
Digital Circuits And Microprocessors
,
1981
.
[9]
William I. Fletcher.
Engineering approach to digital design
,
1980
.