High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies
暂无分享,去创建一个
[1] Tadashi Shibata,et al. Eliminating Metal‐Sputter Contamination in Ion Implanter for Low‐Temperature‐Annealed, Low‐Reverse‐Bias‐Current Junctions , 1995 .
[2] Tadahiro Ohmi,et al. Ultra-low contact resistance metallization by a silicidation technology employing a silicon capping layer for protection against contamination , 1994, Proceedings of 1994 VLSI Technology Symposium.
[3] Jeong-Mo Hwang,et al. Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[4] Tadahiro Ohmi,et al. Current drive enhancement by using high-permittivity gate insulator in SOI MOSFET's and its limitation , 1996 .
[5] M. Tomizawa,et al. Design considerations for thin-film SOI/CMOS device structures , 1989 .
[6] Dimitri A. Antoniadis,et al. Tradeoffs of current drive vs. short-channel effect in deep-submicrometer bulk and SOI MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.
[7] Y. Kado,et al. A High-performance Ultra-thin Quarter-Micron CMOS/SIMOX Technology , 1993, Symposium 1993 on VLSI Technology.
[8] Tadahiro Ohmi,et al. A novel self-aligned surface-silicide passivation technology for reliability enhancement in copper interconnects , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.