A numerical study of scaling issues for trench power MOSFETs

The effect of the scaling down on the electrical performance of trench power MOSFET structures is investigated in this work by means of numerical simulation tools. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. Nowadays, the last scaling efforts provide trench width and distance between two consecutive trenches in the submicron range. The resultant short distance between gates is expected to induce significant modifications in the device electrical performances, since the fully depletion condition will be feasible in the body region. Hence, the influence of the fully depleted body on the on-state resistance, threshold voltage, breakdown voltage, parasitic bipolar transistor and internal capacitances are features of particular interest. Furthermore, device reliability aspects, such as hot-carrier and self-heating effects, are evaluated by numerical simulation in trench power MOSFETs for the first time.

[1]  K. Board,et al.  Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate , 1996 .

[2]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[3]  J. Bokor,et al.  Reliability study of CMOS FinFETs , 2003, IEEE International Electron Devices Meeting 2003.

[4]  Ben Chan,et al.  A new power W-gated trench MOSFET (WMOSFET) with high switching performance , 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

[5]  G. Amaratunga,et al.  The behavior of very high current density power MOSFETs , 1997 .

[6]  S. Banerjee,et al.  Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping , 2002 .

[7]  A. Heringa,et al.  Gate-drain charge analysis for switching in power trench MOSFETs , 2004, IEEE Transactions on Electron Devices.

[8]  Yearn-Ik Choi,et al.  Optimum design for minimum on-resistance of low voltage trench power MOSFET , 2004, Microelectron. J..

[9]  G. Groeseneken,et al.  Hot-carrier degradation phenomena in lateral and vertical DMOS transistors , 2004, IEEE Transactions on Electron Devices.

[10]  Levent Trabzon,et al.  The impact of trench geometry and processing on the performance and reliability of low voltage power UMOSFETs , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[11]  Steve Hall,et al.  Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation , 2003 .

[12]  F. Morancho,et al.  The on-resistance limits of high cell density power MOSFET's , 1997, 1997 21st International Conference on Microelectronics. Proceedings.

[13]  Karl Hess,et al.  MOSFET degradation kinetics and its simulation , 2003 .

[14]  S.S. Wong,et al.  Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI , 1997, IEEE Electron Device Letters.

[15]  Kambiz Vafai,et al.  Modeling of non-uniform heat dissipation and prediction of hot spots in power transistors , 1998 .

[16]  Bing-Yue Tsui,et al.  Trench gate power MOSFETs with retrograde body profile , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[17]  Akio Nakagawa,et al.  30V new fine trench MOSFET with ultra low on-resistance , 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

[18]  Malak Darwish.  Next-generation semiconductors for DC-to-DC converters , 2003, 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440).

[19]  Frederic Allibert,et al.  Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length , 2004 .

[20]  F. N. Masana,et al.  A closed form solution of junction to substrate thermal resistance in semiconductor chips , 1996 .

[21]  Denis Flandre,et al.  Moderate Inversion Model of Ultrathin Double-gate Nmos/soi Transistors , 1995 .

[22]  J. Plummer,et al.  Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 /spl mu/m thick silicon pillars , 1996, 1996 54th Annual Device Research Conference Digest.

[23]  Jin-Gun Koo,et al.  Novel process techniques for fabricating high density trench MOSFETs with self-aligned N/sup +//P/sup +/ source formed on the trench side wall , 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

[24]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[25]  Jaume Roig,et al.  Modeling of non-uniform heat generation in LDMOS transistors , 2005 .

[26]  H. Takagi,et al.  A new vertical power MOSFET structure with extremely reduced on-resistance , 1985, IEEE Transactions on Electron Devices.

[27]  C. Hu,et al.  Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs , 2004 .