Verifying programs with unreliable channels
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[1] Bernhard Steffen,et al. Model Checking for Context-Free Processes , 1992, CONCUR.
[2] Richard M. Karp,et al. Parallel Program Schemata , 1969, J. Comput. Syst. Sci..
[3] Orna Grumberg,et al. Network Grammars, Communication Behaviors and Automatic Verification , 1989, Automatic Verification Methods for Finite State Systems.
[4] A. Prasad Sistla,et al. Reasoning about systems with many processes , 1992, JACM.
[5] Faron Moller,et al. Bisimulation Equivalence is Decidable for Basic Parallel Processes , 1993, CONCUR.
[6] Petr Jancar,et al. Decidability of a Temporal Logic Problem for Petri Nets , 1990, Theor. Comput. Sci..
[7] Mohamed G. Gouda,et al. On deadlock detection in systems of communicating finite state machines , 1987 .
[8] Pierre Wolper,et al. Using partial orders for the efficient verification of deadlock freedom and safety properties , 1991, Formal Methods Syst. Des..
[9] Graham Higman,et al. Ordering by Divisibility in Abstract Algebras , 1952 .
[10] Bengt Jonsson,et al. Deciding Bisimulation Equivalences for a Class of Non-Finite-State Programs , 1989, Inf. Comput..
[11] Edmund M. Clarke,et al. Avoiding the state explosion problem in temporal logic model checking , 1987, PODC '87.
[12] Pierre Wolper,et al. Expressing interesting properties of programs in propositional temporal logic , 1986, POPL '86.
[13] Wang Yi,et al. CCS + Time = An Interleaving Model for Real Time Systems , 1991, ICALP.
[14] Søren Christensen,et al. Bisimulation Equivalence is Decidable for all Context-Free Processes , 2022 .
[15] Bruno Courcelle,et al. On Constructing Obstruction Sets of Words , 1991, Bull. EATCS.
[16] Gregor von Bochmann,et al. Finite State Description of Communication Protocols , 1978, Comput. Networks.
[17] Jan K. Pachl,et al. Protocol Description and Analysis Based on a State Transition Model with Channel Expressions , 1987, PSTV.
[18] Hsu-Chun Yen,et al. Boundedness, Empty Channel Detection, and Synchronization for Communicating Finite Automata , 1986, Theor. Comput. Sci..
[19] Martin Peschke,et al. Design and Validation of Computer Protocols , 2003 .
[20] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[21] E. Clarke,et al. Automatic Veriication of Nite-state Concurrent Systems Using Temporal-logic Speciications. Acm , 1993 .
[22] Zohar Manna,et al. The Temporal Logic of Reactive and Concurrent Systems , 1991, Springer New York.
[23] Keith A. Bartlett,et al. A note on reliable full-duplex transmission over half-duplex links , 1969, Commun. ACM.