Impact of asymmetric dual-k spacers on tunnel field effect transistors

In this paper, we propose a novel device structure for tunneling FETs, based on charge plasma concept, such as junctionless-TFET (JLTFET) and dopingless-TFET (DLTFET) with asymmetric dual-k spacer. Using 2-D simulations, we demonstrate that ON-state current increases significantly with the use of asymmetric dual-k spacers between the gate and p-gate/source in JLTFET and DLTFET. We optimize the spacer length ($$L_\mathrm{S}$$LS) between gate and p-gate/source for these transistors having low-k spacer only. We have employed dual-k spacer, which consists of high-k spacer on gate side and low-k spacer on source side, which could also be interchangeably used. We also optimize the inner high-k spacer length for better analog and digital performance and investigate their impacts on the transistor performance. The simulation results for asymmetric dual-k spacers JLTFET (ADK-JLTFET) offer an improvement of two orders in ON-state current, with point subthreshold slope of 40 mV/dec, and a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio of $$\sim 10^{8}$$∼108. We estimate the improvement in digital performance using ‘$$I_{\mathrm{o}}/C_{\mathrm{in}}$$Io/Cin’ ($$I_{\mathrm{D}}/C_{\mathrm{GG}}$$ID/CGG) and analog performance using unity gain frequency ‘$$f_{\mathrm{T}}$$fT’ as the figure of merit. We observe that the proposed ADK-JLTFET offers 30 times increase in $$I_{\mathrm{o}}/C_{\mathrm{in}}$$Io/Cin and 24 times increase in $$f_{\mathrm{T}}$$fT as compared to JLTFET with only low-k spacer. Due to similar working mechanism, ADK-DLTFET also shows similar improvements.

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