State Reordering for Low Power Combinational Logic

Circuit partition, precomputation and retiming techniques are effective in reducing power consumption of the combinational circuits. In this paper, we propose a methodology to optimize power consumption at combinational logic, named state reordering. The state reordering synthesis flow consists of three phases: first, evenly partition the output patterns based on the Shannon expansion, secondly encode the output vectors of each partition to build an equivalent functional logic. Finally, apply combine algorithm to rearrange the logic function to reduce power consumption and decrease area cost. The validity of our concept is proven by applying it to some MCNC benchmarks with simulation environment.