Investigation on the Effects of Unbalanced Clamping Force on Multichip Press Pack IGBT Modules

Press-pack packaging technology has been widely used in insulated-gate bipolar transistors for high-voltage and high-power density applications. The effects of unbalanced internal pressure, which occurs frequently within large-scale press-pack modules, remain unclear, and thermal parameters within modules cannot be directly measured due to the pressure-type package structure. Current and temperature distribution within 3300 V/1500 A modules are investigated to determine module reliability characteristics and derive future lifetime models using multiphysics models. Unbalanced clamping force causes extremely uneven temperature stress and electrical stress in spatial distribution. It indicates that partial chips must withstand high stresses that cause the initial fatigue of large-scale press-pack modules. Junction temperature difference reaches up to 53.6 °C among chips at chip surface roughness of $1.27~\mu \text{m}$ . This condition shows that the aging of modules will accelerate at the onset of partial chips degradation. Finite-element modeling and equivalent test are utilized to verify the multiphysics model by using single-chip devices in parallel.