A 2.65 W high-fidelity filterless class D audio amplifier using multiple loop filters

The design of a 2.65 W, high-fidelity, filterless Class D audio amplifier in a standard 0.5 μm CMOS technology is proposed in this paper, where an architecture with multiple loop filters is utilized. This structure attenuates residual clock signals around the loop allowing very low total harmonic distortion (THD) and intermodulation distortion to be achieved in conjunction with high power supply rejection ratio (PSRR). The active area of this circuit is about 1.5 × 1.5 mm2. The THD + N is <0.03 % at 1 kHz input frequency and 100 mW output power. The PSRR is −80 dB at 217 Hz and maximum output power at 10 % THD is 2.658 W. A Figure of merit is defined to estimate the excellent performance which can meet the demands of portable communication devices greatly.