Min-Cost Partitioning on a Tree Structure and Applications

We introduce a generalization of the min-cut partitioning problem, called Min-Cost Tree Partitioning, in which the nodes of an hypergraph G are to be mapped on to the vertices of a tree structure T, and the cost function to be minimized is the cost of routing the hyperedges (i.e., the nets) of G on the edges of T. We discuss several interesting VLSI design applications for this problem. We describe an iterative improvement heuristic for solving this problem.

[1]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[2]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[3]  Stephen W. Director,et al.  Mason: A Global Floorplanning Approach for VLSI Design , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .

[5]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[6]  Brian W. Kernighan,et al.  A Procedure for Placement of Standard-Cell VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Inderpal S. Bhandari,et al.  The min-cut shuffle: toward a solution for the global effect problem of min-cut placement , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..