Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor

There is a rapid need to explore circuit designs in the newly emerging technologies to help extend the saturating Moore's Law. This paper presents the optimized design and performance analysis of Dual-X Current Conveyor with the Hybrid CMOS and CNFET technologies at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device and the average power dissipated are chosen as the parameters of reference for carrying out the analysis. Simulations have been carried out using HSPICE simulator at a reduced power supply of ±0.9V.

[1]  Dorra Sellami Masmoudi,et al.  High performance dual-output second and third generation current conveyors and current-mode multifunction filter application , 2009, 2009 6th International Multi-Conference on Systems, Signals and Devices.

[2]  Shahram Minaei,et al.  A new full-wave rectifier circuit employing single dual-X current conveyor , 2008 .

[3]  O. Cicekoglu,et al.  A novel multi-input single-output filter with reduced number of passive elements using single current conveyor , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[4]  A. Toker,et al.  The dual-X current conveyor (DXCCII): a new active device for tunable continuous-time filters , 2003 .

[5]  B. Wilson,et al.  Recent developments in current conveyors and current-mode circuits , 1990 .

[6]  Ali Zeki,et al.  DXCCII-based tunable gyrator , 2005 .

[7]  Jing Guo,et al.  Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics , 2004 .

[8]  H.-S. Philip Wong,et al.  Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  H. Dai,et al.  High performance n-type carbon nanotube field-effect transistors with chemically doped contacts. , 2004, Nano letters.

[10]  Herve Barthelemy,et al.  Composite second-generation current conveyor with reduced parasitic resistance , 1994 .

[11]  R. Chau,et al.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.