차동 전하-전달 증폭기를 이용한 저전력 12 비트 확장계수 A/D 변환기 설계

This paper presents the design, analysis, and simulation results of a 12bit, 1.6KS/s extended counting A/D converter. At first, this converter operates as first-order ΣΔ modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. To reduce power consumption, the ADC uses the comparator which is composed of DCTA(differential charge transfer amplifier) and dynamic latch. With a 0.35㎛ CMOS technology, the simulation results show the SNR of 70㏈ and the power consumption of 200㎼ at a 3.3V supply voltage.