Implementation of a Sliding Memory Plane Image Processor

This paper presents architectures and implementation of a Sliding Memory Plane (SliM) Image Processor to build a SIMD parallel computer. The paper also proposes an enhanced multiplication algorithm to reduce the gate count and the number of cycles. The SliM chip consists of mesh-connected 5×5 PEs. Due to the idea ofsliding, that is, overlapping the inter-PE communication time with the computation time, SliM can greatly reduce the inter-PE communication overhead. In addition, four operations corresponding to ALU, shift, data I/O, and inter-PE communication can be grouped into an instruction to be executed in a cycle simultaneously. The implemented SliM chip operates at 25 MHz and gives 625 MIPS. Because of a mesh topology, a large number of chips can be easily connected to form a SIMD parallel computer. We have implemented the scalable SliM Array Processor and developed parallel algorithms for real-time image processing.

[1]  Jake K. Aggarwal,et al.  A Sliding Memory Plane Array Processor , 1993, IEEE Trans. Parallel Distributed Syst..

[2]  W. Daniel Hillis,et al.  The connection machine , 1985 .

[3]  Xiaobo Li,et al.  On the Communication Complexity of Generalized 2-D Convolution on Array Processors , 1989, IEEE Trans. Computers.

[4]  M. Maresca,et al.  Parallel architectures for vision , 1988 .

[5]  Shin'ichiro Okazaki,et al.  A compact real-time vision system using integrated memory array processor architecture , 1995, IEEE Trans. Circuits Syst. Video Technol..

[6]  Myung Hoon Sunwoo,et al.  A parallel image processor chip for real-time applications , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[7]  Myung Hoon Sunwoo,et al.  Design and implementation of a parallel image processor chip for a SIMD array processor , 1995, Proceedings The International Conference on Application Specific Array Processors.

[8]  Kenneth E. Batcher,et al.  Bit-Serial Parallel Processing Systems , 1982, IEEE Transactions on Computers.

[9]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[10]  John R. Nickolls,et al.  The design of the MasPar MP-1: a cost effective massively parallel computer , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[11]  T. J. Sullivan,et al.  The design of a bit-serial coprocessor to perform multiplication and division on a massively parallel architecture , 1988, Proceedings., 2nd Symposium on the Frontiers of Massively Parallel Computation.

[12]  Richard M. Brown,et al.  The ILLIAC IV Computer , 1968, IEEE Transactions on Computers.

[13]  T. J. Fountain,et al.  The CLIP7A Image Processor , 1988, IEEE Trans. Pattern Anal. Mach. Intell..

[14]  J. Gregory,et al.  The SOLOMON Computer , 1963, IEEE Trans. Electron. Comput..