Analysis of mixed-signal systems with affine arithmetic
暂无分享,去创建一个
[1] Lars Hedrich,et al. Analog circuit sizing based on formal methods using affine arithmetic , 2002, ICCAD 2002.
[2] Christoph Grimm,et al. SystemC-AMS requirements, design objectives and rationale , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[3] Alan Mishchenko,et al. Logic Synthesis for Regular Fabric realized in Quantum Dot Cellular Automata , 2004 .
[4] Klaus Waldschmidt,et al. Semi-Symbolic Modeling and Analysis of Noise in Heterogeneous Systems , 2004, FDL.
[5] K. Maezawa,et al. High-speed and low-power operation of a resonant tunneling logic gate MOBILE , 1998, IEEE Electron Device Letters.
[6] Karl Goser,et al. Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes , 2000, Int. J. Circuit Theory Appl..
[7] Robert O. Winder,et al. Threshold logic , 1971, IEEE Spectrum.
[8] Said F. Al-Sarawi,et al. Low power, high speed, charge recycling CMOS threshold logic gate , 2001 .
[9] Tsutomu Sasao,et al. Switching Theory for Logic Synthesis , 1999, Springer US.
[10] Alberto L. Sangiovanni-Vincentelli,et al. Modeling digital substrate noise injection in mixed-signal IC's , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Yoshihito Amemiya,et al. Single-Electron Majority Logic Circuits , 1997 .
[12] Robert K. Brayton,et al. Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[13] Rob A. Rutenbar,et al. Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[14] C. Lageweg,et al. Single electron encoded latches and flip-flops , 2004, IEEE Transactions on Nanotechnology.
[15] Michael L. Dertouzos,et al. Threshold Logic: A Synthesis Approach , 1965 .
[16] Dominique Cansell,et al. Integration of the proof process in the system development through refinement steps , 2002 .
[17] Gerald E. Sobelman,et al. CMOS circuit design of threshold gates with hysteresis , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[18] Christoph Grimm. Modeling and refinement of mixed-signal systems with systemC , 2003 .
[19] Thomas A. Henzinger,et al. HYTECH: The Cornell HYbrid TECHnology Tool , 1994, Hybrid Systems.
[20] B. Rumpe,et al. Roots of Refactoring , 2001 .
[21] Alberto L. Sangiovanni-Vincentelli,et al. LSAT-an algorithm for the synthesis of two level threshold gate networks , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[22] Maria J. Avedillo,et al. Multi-threshold threshold logic circuit design using resonant tunnelling devices , 2003 .
[23] Pinaki Mazumder,et al. Resonant tunneling diodes: models and properties , 1998, Proc. IEEE.
[24] Klaus Waldschmidt,et al. A New Method for Modeling and Analysis of Accuracy and Tolerances in Mixed-Signal Systems , 2003, FDL.
[25] Maria J. Avedillo,et al. Low-power CMOS threshold-logic gate , 1995 .
[26] Stamatis Vassiliadis,et al. A linear threshold gate implementation in single electron technology , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.