Gate-level test generation for sequential circuits

This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques for sequential circuits. The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail. The relationship between gate-level sequential circuit ATPG and the partial scan design is also discussed.

[1]  P. Goel.  AN IMPLICIT ENUMERATION ALGORITHM TO GENERATE TESTS FOR COMBINATIONAL LOGIC CIRCUITS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[2]  Kwang-Ting Cheng,et al.  Automatic generation of functional vectors using the extended finite state machine model , 1996, TODE.

[3]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[4]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[7]  Srinivas Devadas,et al.  Redundancies and don't cares in sequential logic synthesis , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[8]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[9]  Miron Abramovici,et al.  Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") , 1994, Proceedings., International Test Conference.

[10]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[12]  Irith Pomeranz,et al.  LOCSTEP: a logic-simulation-based test generation procedure , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Carl Pixley.  A Computation Theory and Implementation of Sequential Hardware Equivalence , 1990, CAV.

[14]  Michael S. Hsiao,et al.  Automatic test generation using genetically-engineered distinguishing sequences , 1996, Proceedings of 14th VLSI Test Symposium.

[15]  Carl Pixley,et al.  Minimum Length Synchronizing Sequences of Finite State Machine , 1993, 30th ACM/IEEE Design Automation Conference.

[16]  Irith Pomeranz,et al.  The Multiple Observation Time Test Strategy , 1992, IEEE Trans. Computers.

[17]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[18]  Fabio Somenzi,et al.  Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Heinrich Theodor Vierhaus,et al.  FOGBUSTER: an efficient algorithm for sequential test generation , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[20]  Janusz Rajski,et al.  Complexity of sequential ATPG , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[21]  Vishwani D. Agrawal,et al.  Unified Methods for VLSI Simulation and Test Generation , 1989 .

[22]  Thomas J. Snethen.  Simulator-oriented fault test generator , 1988, 25 years of DAC.

[23]  Melvin A. Breuer,et al.  Procedures for Eliminating Static and Dynamic Hazards in Test Generation , 1974, IEEE Transactions on Computers.

[24]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[25]  Sudhakar M. Reddy,et al.  A new test generation method for sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[26]  Srimat T. Chakradhar,et al.  Redundancy removal and test generation for circuits with non-Boolean primitives , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[27]  Peter Muth,et al.  A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.

[28]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[29]  Jacob A. Abraham,et al.  Functional Testing of Microprocessors , 1984, IEEE Transactions on Computers.

[30]  Melvin A. Breuer,et al.  Functional Level Primitives in Test Generation , 1980, IEEE Transactions on Computers.

[31]  Chi W. Yau,et al.  An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[32]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  Kwang-Ting Cheng,et al.  A functional fault model for sequential machines , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Janak H. Patel,et al.  A signal-driven discrete relaxation technique for architectural level test generation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[35]  J. Paul Roth,et al.  A Heuristic Algorithm for the Testing of Asynchronous Circuits , 1971, IEEE Transactions on Computers.

[36]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[37]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[38]  S. G. Chappell.  Lamp: Automatic test generation for asynchronous digital circuits , 1974 .

[39]  Jacob A. Abraham,et al.  Test generation for digital systems , 1986 .

[40]  Janak H. Patel,et al.  Architectural level test generation for microprocessors , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[41]  Lalit M. Patnaik,et al.  A Simulation-Based Test Generation Scheme Using Genetic Algorithms , 1993, The Sixth International Conference on VLSI Design.

[42]  Masahiko Kawamura,et al.  Test generation by activation and defect-drive (TEGAD) , 1985, Integr..

[43]  Michael H. Schulz,et al.  ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[44]  Bernd Becker,et al.  On the (non-)resetability of synchronous sequential circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[45]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[46]  Sundaram Seshu,et al.  On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..

[47]  Daniel G. Saab,et al.  CRIS: A test cultivation program for sequential VLSI circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[48]  Edward P. Hsieh,et al.  Checking Experiments ror Sequential Machines , 1971, IEEE Transactions on Computers.

[49]  Daniel G. Saab,et al.  On the initialization of sequential circuits , 1994, Proceedings., International Test Conference.

[50]  Zvi Kohavi,et al.  Checking experiments for sequential machines , 1974, Inf. Sci..

[51]  Daniel G. Saab,et al.  Iterative simulation-based Genetics + Deterministic Techniques = Complete AtPG , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[52]  Elizabeth M. Rudnick,et al.  Application of simple genetic algorithms to sequential circuit test generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[53]  Irith Pomeranz,et al.  LOCSTEP: a logic simulation based test generation procedure , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[54]  Hiroshi Kubo,et al.  A procedure for generating test sequences to detect sequential circuit failures , 1968 .

[55]  Melvin A. Breuer.  The Effects of Races, Delays, and Delay Faults on Test Generation , 1974, IEEE Transactions on Computers.

[56]  F. C. Hennine.  Fault detecting experiments for sequential circuits , 1964, SWCT 1964.

[57]  Kwang-Ting Cheng,et al.  Redundancy removal for sequential circuits without reset states , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[58]  Alexander Miczo,et al.  Digital logic testing and simulation , 1986 .

[59]  Paolo Prinetto,et al.  An automatic test pattern generator for large sequential circuits based on Genetic Algorithms , 1994, Proceedings., International Test Conference.

[60]  Carl Pixley,et al.  Calculating resettability and reset sequences , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[61]  Fredrick J. Hill,et al.  SCIRTSS: A Search System for Sequential Circuit Test Sequences , 1977, IEEE Transactions on Computers.

[62]  Michael S. Hsiao,et al.  Alternating strategies for sequential circuit ATPG , 1996, Proceedings ED&TC European Design and Test Conference.

[63]  Kozo Kinoshita,et al.  Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals , 1983, 20th Design Automation Conference Proceedings.

[64]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[65]  Kewal K. Saluja,et al.  An Efficient Algorithm for Sequential Circuit Test Generation , 1993, IEEE Trans. Computers.

[66]  John P. Hayes,et al.  High-level test generation using symbolic scheduling , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[67]  Paolo Prinetto,et al.  Advanced techniques for GA-based sequential ATPGs , 1996, Proceedings ED&TC European Design and Test Conference.

[68]  Irith Pomeranz,et al.  Classification of Faults in Synchronous Sequential Circuits , 1993, IEEE Trans. Computers.

[69]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[70]  Seh-Woong Jeong,et al.  Exact calculation of synchronizing sequences based on binary decision diagrams , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[71]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[72]  Jacob A. Abraham,et al.  Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.

[73]  Srinivas Devadas,et al.  Sequential test generation at the register-transfer and logic levels , 1991, DAC '90.

[74]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[75]  Ralph Marlett,et al.  EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits , 1978, 15th Design Automation Conference.

[76]  Srinivas Devadas,et al.  Redundancies and don't cares in sequential logic synthesis , 1990, J. Electron. Test..

[77]  Kwang-Ting Cheng,et al.  On the over-specification problem in sequential ATPG algorithms , 1992, DAC '92.

[78]  Seh-Woong Jeong,et al.  Synchronizing sequences and symbolic traversal techniques in test generation , 1993, J. Electron. Test..

[79]  Irith Pomeranz,et al.  On achieving a complete fault coverage for sequential machines using the transition fault model , 1991, 28th ACM/IEEE Design Automation Conference.

[80]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[81]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[82]  Vishwani D. Agrawal,et al.  Combinational ATPG theorems for identifying untestable faults in sequential circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[83]  Vishwani D. Agrawal,et al.  Tutorial test generation for VLSI chips , 1988 .

[84]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[85]  Krishan K. Sabnani,et al.  A Protocol Test Generation Procedure , 1988, Comput. Networks.

[86]  Janak H. Patel,et al.  PROOFS: a fast, memory efficient sequential circuit fault simulator , 1990, 27th ACM/IEEE Design Automation Conference.

[87]  Elizabeth M. Rudnick,et al.  Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation , 1995, 32nd Design Automation Conference.

[88]  Carl Pixley.  Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence , 1990, CAV.