A Power Optimized Pipelined Analog-to-Digital Converter Design in Deep Sub-Micron CMOS Technology

[1]  Yuji Gendai,et al.  An 8b 500MHz ADC , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  P. Gray,et al.  High-frequency CMOS switched-capacitor filters for communications application , 1983 .

[3]  Wenhua Yang,et al.  A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input , 2001, IEEE J. Solid State Circuits.

[4]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[5]  Ardie G. W. Venes,et al.  An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing , 1996 .

[6]  Bang-Sup Song,et al.  A 15 b 5 MSample/s low-spurious CMOS ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[7]  Hae-Seung Lee,et al.  A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement , 1993 .

[8]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[9]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[10]  Y. Akazawa,et al.  Jitter analysis of high-speed sampling systems , 1990 .

[11]  Bang-Sup Song,et al.  A 10-b 20-Msample/s low-power CMOS ADC , 1995, IEEE J. Solid State Circuits.

[12]  Eric A. Vittoz,et al.  Low-power design: ways to approach the limits , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[13]  Andrew Masami Abo,et al.  Design for Reliability of Low-voltage, Switched-capacitor Circuits , 1999 .

[14]  Jesper Steensgaard,et al.  Bootstrapped low-voltage analog switches , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[15]  Chenming Hu,et al.  Switch-induced error voltage on a switched capacitor , 1984 .

[16]  K. Bacrania,et al.  A 10-b 40-Msample/s BiCMOS A/D converter , 1996 .

[17]  Bruce A. Wooley,et al.  The effects of switching noise on an oversampling A/D converter , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[18]  T. Kuyel,et al.  A 14 b 40 MSample/s pipelined ADC with DFCA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[19]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[20]  Bang-Sup Song,et al.  A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter , 1995, IEEE J. Solid State Circuits.

[21]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[22]  John P. Uyemura.  Introduction to CMOS , 1992 .

[23]  Pieter Rombouts,et al.  A digital error-averaging technique for pipelined A/D conversion , 1998 .

[24]  Behzad Razavi,et al.  A 12-b 5-Msample/s two-step CMOS A/D converter , 1992 .

[25]  I. Mehr,et al.  A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[26]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[27]  Kwang Young Kim,et al.  A 10-b, 100-MS/s CMOS A/D converter , 1997 .

[28]  L. Singer,et al.  A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[29]  Kari Halonen,et al.  A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[30]  R. C. Taft,et al.  A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V , 2001 .

[31]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[32]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[33]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[34]  Stephen H. Lewis,et al.  Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications , 1992 .

[35]  Bram Nauta,et al.  A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter , 1995 .

[36]  Kyoung-Ho Moon,et al.  A 10 bit 30 MSPS CMOS A/D converter for a high performance video application system , 1997 .

[37]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[38]  Howard C. Luong,et al.  Power optimization for pipeline analog-to-digital converters , 1999 .

[39]  Bruce A. Wooley,et al.  Second-order sigma-delta modulation for digital-audio signal acquisition , 1991 .

[40]  K. Bacrania,et al.  A 14 b 20 MSample/s CMOS pipelined ADC , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).