A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic Processing

In this paper a novel Reconfigurable Arithmetic FPGA (RA-FPGA) architecture is presented. The FPGA employs novel logic cell structures (called Configurable Arithmetic Units CAUs) and an interconnection framework appropriate for high performance computer arithmetic. The FPGA architecture is both flexible, reconfigurable and is optimised for bit parallel processing of wide data. The proposed architecture is also scaleable supporting data of varying word length. Performance characteristics based on a 0.7Μm CMOS process is presented.