Optimal Drive Signals Design and Implementation in CPLD for Medium Voltage Three-level Inverter Equipped With IGCTS

IGCT-based(Integrated Gate Commutated Thyristor)medium voltage three-level inverters are widely used in industry.To ensure the value of dead time and minimum pulse width,the PWM drive signals of IGCT require processing before entering IGCT gate units.This paper presents a novel drive signals optimal method for a MVA three-level inverter.The process of the design includes parameters computation and flow implementation,which are based on the IGCT characteristic,circuit parameters and control requirements.Dual-CPLD(Complex Programmable Logic Device)structure is employed to implement optimal flow design and provides a fast faults handling.This method is verified by the results of simulation and experiments,which is an efficient improvement for the reliability and security of inverters.