Boundary element methods for capacitance and substrate resistance calculations in a VLSI layout verification package

In this paper we describe the application of the Boundary Element Method to the layout verification of VLSI Designs. We describe the methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Green's functions. Emphasis is on computational efficiency and practical accuracy. The methods are implemented in the layout extractor Space (van der Meijs [1 ]).