The characterization and application of a low resource FPGA-based time to digital converter☆

Abstract Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured.

[1]  Jinyuan Wu,et al.  Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs , 2009, IEEE Transactions on Nuclear Science.

[2]  F. Happacher,et al.  Physics with the KLOE-2 experiment at the upgraded DAΦNE , 2010, 1003.3868.

[3]  Stephan Henzler,et al.  Time-to-Digital Converters , 2010 .

[4]  J. Kalisz,et al.  Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution , 1997 .

[5]  John F. Wakerly,et al.  Digital design - principles and practices , 1990, Prentice Hall Series in computer engineering.

[6]  Mark W. Drigert,et al.  A high-resolution, multi-stop, time-to-digital converter for nuclear time-of-flight measurements , 2006 .

[7]  Peter Zipf,et al.  A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA) , 2011, 2011 IEEE Nuclear Science Symposium Conference Record.

[8]  J. J. Williams,et al.  High-precision TDC in an FPGA using a 192 MHz quadrature clock , 2002, 2002 IEEE Nuclear Science Symposium Conference Record.

[10]  Jian Song,et al.  A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays , 2006, IEEE Transactions on Nuclear Science.

[11]  Guo-Ruey Tsai,et al.  FPGA-Based High Area Efficient Time-To-Digital IP Design , 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

[12]  R. Nutt.  Digital Time Intervalometer , 1968 .

[13]  F. Gonnella,et al.  The KLOE-2 High Energy Tagger detector , 2012, 1206.0680.

[14]  Jinyuan Wu,et al.  ADC and TDC implemented using FPGA , 2007, 2007 IEEE Nuclear Science Symposium Conference Record.

[15]  Shubin Liu,et al.  The 10-ps Multitime Measurements Averaging TDC Implemented in an FPGA , 2011, IEEE Transactions on Nuclear Science.

[16]  L. Iafolla,et al.  FPGA-based time to digital converter and data acquisition system for high energy tagger of KLOE-2 experiment , 2013 .

[17]  D. Badoni,et al.  Gamma–gamma tagging system for KLOE2 experiment , 2010 .

[18]  Jinyuan Wu,et al.  The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay , 2008, 2008 IEEE Nuclear Science Symposium Conference Record.

[19]  Shubin Liu,et al.  A fully fledged TDC implemented in field-programmable-gate-arrays , 2009, 2009 16th IEEE-NPSS Real Time Conference.

[20]  Józef Kalisz,et al.  Review of methods for time interval measurements with picosecond resolution , 2004 .

[21]  M. Traxler,et al.  A High-Resolution ( ${< 10}~{\rm ps}$ RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA) , 2010, IEEE Transactions on Nuclear Science.