A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.

[1]  H. Pilo,et al.  An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage , 2007, IEEE Journal of Solid-State Circuits.

[2]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[3]  Young-Hyun Jun,et al.  A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Ali Sheikholeslami,et al.  A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme , 2003, IEEE J. Solid State Circuits.

[5]  Koji Nii,et al.  1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[6]  Sasaki Takahiko,et al.  A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver , 2009 .

[7]  Meng-Fan Chang,et al.  A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications , 2009, IEEE Journal of Solid-State Circuits.

[8]  Meng-Fan Chang,et al.  A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications , 2009, 2009 Symposium on VLSI Circuits.

[9]  Naveen Verma,et al.  A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Y.H. Chen,et al.  A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs , 2008, 2008 IEEE Symposium on VLSI Circuits.

[11]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[12]  Shuhei Tanakamaru,et al.  Improvement of Read Margin and Its Distribution by $V_{\rm TH}$ Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection , 2011, IEEE Journal of Solid-State Circuits.

[13]  Chingwei Yeh,et al.  High-Speed and Low-Power Design Techniques for TCAM Macros , 2008, IEEE Journal of Solid-State Circuits.

[14]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[15]  Wei Hwang,et al.  A 65 nm 0.165 fJ/Bit/Search 256 $\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables , 2011, IEEE Journal of Solid-State Circuits.

[16]  Meng-Fan Chang,et al.  A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques , 2013, IEEE Journal of Solid-State Circuits.

[17]  S. Shimada,et al.  Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[18]  Meng-Fan Chang,et al.  A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme , 2011, IEEE Journal of Solid-State Circuits.

[19]  Meng-Fan Chang,et al.  A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme , 2017, IEEE Journal of Solid-State Circuits.

[20]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[21]  Meng-Fan Chang,et al.  A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing , 2016, IEEE Journal of Solid-State Circuits.

[22]  Jinn-Shyan Wang,et al.  An AND-type match-line scheme for high-performance energy-efficient content addressable memories , 2006 .

[23]  H. Fujiwara,et al.  An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment , 2007, 2007 IEEE Symposium on VLSI Circuits.

[24]  Igor Arsovski,et al.  1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50% , 2018, IEEE Journal of Solid-State Circuits.

[25]  Meng-Fan Chang,et al.  17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[26]  Hiroyuki Kawai,et al.  A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[27]  Meng-Fan Chang,et al.  A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing , 2017, IEEE Journal of Solid-State Circuits.

[28]  Tien-Fu Chen,et al.  An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices , 2009, IEEE J. Solid State Circuits.

[29]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[30]  Peilin Song,et al.  1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing , 2013, 2013 Symposium on VLSI Circuits.

[31]  Koji Nii,et al.  A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations , 2008, IEEE Journal of Solid-State Circuits.

[32]  Meng-Fan Chang,et al.  7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[33]  Zhao Chuan Lee,et al.  A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI , 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[34]  H. Yamauchi,et al.  A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses , 2008, IEEE Journal of Solid-State Circuits.

[35]  Meng-Fan Chang,et al.  A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme , 2010, 2010 Symposium on VLSI Circuits.

[36]  Tien-Fu Chen,et al.  An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices , 2009, IEEE Journal of Solid-State Circuits.

[37]  Meng-Fan Chang,et al.  Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme , 2014, IEEE Journal of Solid-State Circuits.