Optimized RTL design and implementation of LZW algorithm for high bandwidth applications

This paper presents a high-speed low-complexity Register Transfer Logic (RTL) design and implementation of the lossless Lempel-Ziv- Welch (LZW) algorithm on Xilinx Virtex II device family for High Bandwidth Applications. Comparative analysis of the proposed design with the established commercial data compression and decompression accelerators show that the proposed design offers comparatively high throughput 1.42 Gbits/s, elevated throughput/slice value 151.8 Kbytes/s/slice and lower operational power requirements 333 mW. Streszczenie. W artykule zaprezentowano nieskomplikowany, wysokiej czestotliwości projekt obwodu RTL oraz bezstratny algorytm LZW z ukladem Xilinx Virtex II. Porownano zaproponowany uklad z komercyjnymi ukladami kompresji i stwierdzono, ze umozliwia on przepustowośc 1.42 Gbit/s przy poborze mocy 333 mW. (Optymalizowany uklad RTL i algorytm LZW w zastosowaniach szerokopasmowych).

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