Compiler Optimization for Configurable Accelerators

ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C to HDL compiler targeting FPGA and CSOC (Configurable System On a Chip) architectures. ROCCC system is built on the SUIFMACHSUIF compiler infrastructure. Our system first identifies frequently executed kernel loops inside programs and then compiles them to VHDL after optimizing the kernels to make best use of FPGA resources. This paper presents an overview of the ROCCC project as well as optimizations performed inside the ROCCC compiler.