Analyzing concurrency in streaming applications

We present a concurrency model that allows reasoning about concurrency in executable specifications of streaming applications. It provides measures for five different concurrency properties. The aim of the model is to provide insight into concurrency bottlenecks in an application and to provide global direction when performing implementation-independent concurrency optimization. The model focuses on task-level concurrency. A concurrency optimization method and a prototype implementation of a supporting analysis tool have been developed. We use the model and tool to optimize the concurrency in a number of multimedia applications. The results show that the concurrency model allows target-architecture-independent concurrency optimization.

[1]  K. Keutzer,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[3]  Ed F. Deprettere,et al.  The Artemis Architecture Workbench , 2000 .

[4]  Michel Raynal,et al.  Synchronization and concurrency measures for distributed computations , 1992, [1992] Proceedings of the 12th International Conference on Distributed Computing Systems.

[5]  Francky Catthoor,et al.  Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems , 1999, Springer US.

[6]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[7]  Antonino Mazzeo,et al.  Efficiency measurements in heterogeneous distributed computing systems: from theory to practice , 1998 .

[8]  Viktor K. Prasanna,et al.  Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation , 2002, LCTES/SCOPES '02.

[9]  Loïc Hélouët,et al.  Decomposition of Message Sequence Charts , 2000, SAM.

[10]  Ali R. Hurson,et al.  General-purpose systolic arrays , 1993, Computer.

[11]  Mohammed Ghanbari.  Video coding for low bit rate communications (H.263) , 2003 .

[12]  Erwin A. de Kock,et al.  YAPI: application modeling for signal processing systems , 2000, Proceedings 37th Design Automation Conference.

[13]  K. Ravindran,et al.  Extraction of logical concurrency in distributed applications , 1993, [1993] Proceedings. The 13th International Conference on Distributed Computing Systems.

[14]  Leslie Lamport,et al.  Time, clocks, and the ordering of events in a distributed system , 1978, CACM.

[15]  Matthias Gries,et al.  Methods for evaluating and covering the design space during early design development , 2004, Integr..

[16]  Kurt Keutzer,et al.  Mapping Concurrent Applications onto Architectural Platforms , 2003, Networks on Chip.

[17]  Edward A. Lee,et al.  Dataflow process networks , 2001 .

[18]  Andy D. Pimentel,et al.  A multiobjective optimization model for exploring multiprocessor mappings of process networks , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[19]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[20]  Edward A. Lee,et al.  A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Erwin A. de Kock.  Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study , 2002, ISSS.

[22]  Luciano Lavagno,et al.  Metropolis: An Integrated Electronic System Design Environment , 2003, Computer.

[23]  Vaughan R. Pratt,et al.  Modeling concurrency with partial orders , 1986, International Journal of Parallel Programming.

[24]  Ed F. Deprettere,et al.  A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems , 2001, J. VLSI Signal Process..

[25]  David B. Skillicorn,et al.  Models and languages for parallel computation , 1998, CSUR.

[26]  P. Stravers,et al.  Homogeneous multiprocessing and the future of silicon design paradigms , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[27]  Rudy Lauwereins,et al.  Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java , 2003, SCOPES.

[28]  Jeffrey Bokor,et al.  International Symposium on VLSI Technology, Systems, and Applications, Proceedings , 1997 .

[29]  Gilles Kahn,et al.  Coroutines and Networks of Parallel Processes , 1977, IFIP Congress.

[30]  E. Rijpkema,et al.  Compaan: deriving process networks from Matlab for embedded signal processing architectures , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).

[31]  Amir Pnueli,et al.  Marked Directed Graphs , 1971, J. Comput. Syst. Sci..