Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs

In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This perturbation uses a technique of enumerating block positions, which is implemented based on the floorplan-representation sequence pair. The proposed perturbation method can greatly accelerate searching-based algorithms, such as simulated annealing, by skipping many solutions that fail to meet the fixed-outline constraint. Moreover, based on the analysis of the diverse objective functions used in the existing research works, we suggest for the FOFP a new objective function which is still effective when combined with other objectives. Experimental results show that, if area and wirelength are optimized simultaneously, using less time, the proposed method obtains much higher average success rate for the FOFP with various aspect ratios, while the wirelength with the fixed-outline constraint is reduced by 20% on average, compared with the latest fixed-outline floorplanners. On the other hand, we validated once more by experiments that an aspect ratio close to one is beneficial to wirelength, and hence, a larger area weight is necessary for the FOFP with a larger aspect ratio to ensure feasible solutions.

[1]  Andrew B. Kahng,et al.  On wirelength estimations for row-based placement , 1998, ISPD '98.

[2]  Yao-Wen Chang,et al.  IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[3]  Igor L. Markov,et al.  Are floorplan representations important in digital design? , 2005, ISPD '05.

[4]  Yao-Wen Chang,et al.  Modern floorplanning based on fast simulated annealing , 2005, ISPD '05.

[5]  Jarrod A. Roy,et al.  Unification of partitioning, placement and floorplanning , 2004, ICCAD 2004.

[6]  Andrew B. Kahng,et al.  Classical floorplanning harmful? , 2000, ISPD '00.

[7]  Jarrod A. Roy,et al.  Min-cut floorplacement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Yoji Kajitani,et al.  Fixed-outline floorplanning with constraints through instance augmentation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[9]  Yao-Wen Chang,et al.  Modern floorplanning based on B/sup */-tree and fast simulated annealing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Igor L. Markov,et al.  Fixed-outline floorplanning through better local search , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[12]  Martin D. F. Wong,et al.  Fast evaluation of sequence pair in block placement by longest common subsequence computation , 2000, DATE '00.

[13]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Chang-Tzu Lin,et al.  Robust fixed-outline floorplanning through evolutionary search , 2004, ASP-DAC.

[15]  Takeshi Yoshimura,et al.  Floorplanning using a tree representation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..