Cryocooled Wideband Digital Channelizing RF Receiver Based on Low-Pass ADC

We have demonstrated a digital receiver performing direct digitization of radio frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor All-Digital Receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass delta modulator with phase modulation- demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4.5 kA/cm 2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed. To our knowledge this is the fastest digital receiver demonstrated to date.