High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

This paper presents a high speed Single-Stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding Read-Out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and Read-Out circuit is about 300µm2.

[1]  Seung-Hoon Lee,et al.  A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Atila Alvandpour,et al.  A CMOS comparator with reduced kick-back for a 4-6-bit 3-GS/S flash ADC in a 90NM process. , 2007 .

[3]  Riyan Wang,et al.  A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters , 2007, 2007 International Workshop on Anti-Counterfeiting, Security and Identification (ASID).

[4]  Yin-tang Yang,et al.  A novel 1.25GSPS ultra high-speed comparator in 0.18μm CMOS , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[5]  L. Bouzerara,et al.  High Speed Low Power CMOS Comparator Dedicated to 10it, 20MHz Pipeline ADCs for RF Applications , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

[6]  Horst Zimmermann,et al.  A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  F. Borghetti,et al.  A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors , 2008, IEEE Journal of Solid-State Circuits.

[8]  Pamela Abshire,et al.  A 1.2-GHz comparator with adaptable offset in 0.35-μm CMOS , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Shahriar Mirabbasi,et al.  A 0.35 /spl mu/m CMOS comparator circuit for high-speed ADC applications , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[10]  A. Baschirotto,et al.  A Clock-Less 10-bit Pipeline A/D Converter for Self-Triggered Sensors , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[11]  A. Alvandpour,et al.  A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process , 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

[12]  L. Bouzerara,et al.  High Speed Low Power CMOS Comparator for Pipeline ADCs , 2006, 2006 25th International Conference on Microelectronics.