Reliability of ultrathin gate oxides for ULSI devices

[1]  Chun-Yen Chang,et al.  TEMPERATURE-ACCELERATED DIELECTRIC BREAKDOWN IN ULTRATHIN GATE OXIDES , 1999 .

[2]  D. Sohn,et al.  In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline Si , 1998 .

[3]  Y. Hanaoka,et al.  Improving gate oxide integrity (GOI) of a W/WNx/dual-poly Si stacked-gate by using wet-hydrogen oxidation in 0.14-/spl mu/m CMOS devices , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[4]  G.A. Brown,et al.  CMOS metal replacement gate transistors using tantalum pentoxide gate insulator , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[5]  A. Amerasekera,et al.  Antenna device reliability for ULSI processing , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[6]  T. Yamamoto,et al.  An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[7]  T. Ma,et al.  High quality ultra-thin TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric for giga scale MOS technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[8]  M.D. Morris,et al.  Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[9]  K. Taniguchi,et al.  A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structures , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[10]  W. Abadeer,et al.  Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[11]  Xin Guo,et al.  Reduced gate leakage current and boron penetration of 0.18 /spl mu/m 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectric , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[12]  Y. Akasaka,et al.  Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[13]  J. Stathis,et al.  Reliability projection for ultra-thin oxides at low voltage , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[14]  K. Zawadzki,et al.  Effect of barrier layer on the electrical and reliability characteristics of high-k gate dielectric films , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[15]  R. Fleming,et al.  Advanced dielectrics for gate oxide, DRAM and RF capacitors , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[16]  P. Vande Voorde,et al.  Boron diffusion and penetration in ultrathin oxide with poly-Si gate , 1998, IEEE Electron Device Letters.

[17]  Shoji Otaka,et al.  RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[18]  K. Evans-Lutterodt,et al.  Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[19]  K. Ahmed,et al.  Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[20]  Srikanth Krishnan,et al.  Process-induced damage-a study of hydrogen and deuterium passivation , 1998, 1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).

[21]  R. Degraeve,et al.  Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures? , 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

[22]  Guido Groeseneken,et al.  On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers , 1998 .

[23]  T. Tamagawa,et al.  High Quality Ultra-thin TiOJSi3N4 Gate Dielectric for Giga Scale MOS Technology , 1998 .

[24]  Horng-Chih Lin,et al.  Characterization of plasma charging damage in ultrathin gate oxides , 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

[25]  X. Aymerich,et al.  Switching behavior of the soft breakdown conduction characteristic in ultra-thin (<5 nm) oxide MOS capacitors , 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

[26]  Hongfa Luan,et al.  Ultra Thin (<20@ CVD Si3N4 Gate Dielectric for Deep-Sub-Micron CMOS Devices , 1998 .

[27]  Dong Kyun Sohn,et al.  In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline Si , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[28]  D. Hwang,et al.  Ultra-thin gate dielectrics: they break down, but do they fail? , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[29]  K. Tokashiki,et al.  Reliability of thin gate oxide under plasma charging caused by antenna topography-dependent electron shading effect , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[30]  T. Ohguro,et al.  A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[31]  J.P. McVittie.  Process charging in ULSI: mechanisms, impact and solutions , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[32]  S. Crowder,et al.  Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[33]  M. Rodder,et al.  Assessment of charge-induced damage to ultra-thin gate MOSFETs , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[34]  A. Chatterjee,et al.  Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[35]  J. Mogab,et al.  Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetration , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[36]  A. Agarwal,et al.  Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[37]  Yuan Taur,et al.  CMOS devices below 0.1 /spl mu/m: how high will performance go? , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[38]  Flat-band voltage shifts in p-MOS devices caused by carrier activation in p/sup +/-polycrystalline silicon and boron penetration , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[39]  G.A. Brown,et al.  Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[40]  A.H. Montree,et al.  Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[41]  C. Salm,et al.  Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[42]  Han,et al.  Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/) , 1997, 1997 Symposium on VLSI Technology.

[43]  Ma,et al.  Ultra-thin Silicon Nitride Gate Dielectric For Deep-sub-micron CMOS Devices , 1997, 1997 Symposium on VLSI Technology.

[44]  Chi,et al.  A Novel Low-temperature Gate Oxynitride For CMOS Technologies , 1997, 1997 Symposium on VLSI Technology.

[45]  Sugii,et al.  Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs , 1997, 1997 Symposium on VLSI Technology.

[46]  Douglas A. Buchanan,et al.  Reliability and integration of ultra-thin gate dielectrics for advanced CMOS , 1997 .

[47]  Chenming Hu,et al.  Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling , 1997, IEEE Electron Device Letters.

[48]  P. Marcoux,et al.  Scalability Of Plasma Damage With Gate Oxide Thickness , 1997, 2nd International Symposium on Plasma Process-Induced Damage.

[49]  S. Jacobs,et al.  Effect Of MOS Device Scaling On Process Induced Gate Charging , 1997, 2nd International Symposium on Plasma Process-Induced Damage.

[50]  Ming-Yin Hao,et al.  Impact of boron penetration at P/sup +/-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies , 1997, IEEE Electron Device Letters.

[51]  Horng-Chih Lin,et al.  Resist-related damage on ultrathin gate oxide during plasma ashing , 1997 .

[52]  Y. Taur,et al.  Modeling and Characterization of n+- and p+-Polysilicon-Gated Ultra Thin Oxides (21-26 A) , 1997 .

[53]  Chenming Hu,et al.  Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology , 1997, 1997 Symposium on VLSI Technology.

[54]  Dennis L. Polla,et al.  Leakage current and electrical breakdown in metal‐organic chemical vapor deposited TiO2 dielectrics on silicon substrates , 1996 .

[55]  C. Hu.  Gate oxide scaling limits and projection , 1996 .

[56]  S. Krishnan,et al.  Inductively coupled plasma (ICP) metal etch damage to 35-60 A gate oxide , 1996, International Electron Devices Meeting. Technical Digest.

[57]  E. Morifuji,et al.  High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs , 1996, International Electron Devices Meeting. Technical Digest.

[58]  Horng-Chih Lin,et al.  Characterization of Antenna Effect by Nondestructive Gate Current Measurement , 1996 .

[59]  S. Shimizu,et al.  Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[60]  C. Hu,et al.  A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient , 1996, Proceedings of 1st International Symposium on Plasma Process-Induced Damage.

[61]  Alan Mathewson,et al.  Test structure for investigating activated doping concentrations in polycrystalline silicon , 1996, Proceedings of International Conference on Microelectronic Test Structures.

[62]  Toshimasa Matsuoka,et al.  Direct tunneling N/sub 2/O gate oxynitrides for low-voltage operation of dual gate CMOSFETs , 1995, Proceedings of International Electron Devices Meeting.

[63]  Chenming Hu,et al.  High endurance ultra-thin tunnel oxide for dynamic memory application , 1995, Proceedings of International Electron Devices Meeting.

[64]  Shih-Han Hung,et al.  A comprehensive study of suppression of boron penetration by amorphous-Si gate in P/sup +/-gate PMOS devices , 1995 .

[65]  M. Heyns,et al.  Soft Breakdown of Ultra-Thin Gate Oxide Layers , 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

[66]  K. P. Cheung.  A new method to monitor gate-oxide reliability degradation , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[67]  D. Wristers,et al.  Recent developments in ultra thin oxynitride gate dielectrics , 1995 .

[68]  T. Chao,et al.  Nitridation of the stacked poly-Si gate to suppress the boron penetration in pMOS , 1995 .

[69]  Kenji Yoneda,et al.  The Influence of Medium Dose Ion Implantation on the Reliability of Thin Gate Oxide , 1995 .

[70]  Dim-Lee Kwong,et al.  Suppressed Process-Induced Damage in N2O-annealed SiO2 Gate Dielectrics , 1995 .

[71]  Tan Fu Lei,et al.  Nitridation of the stacked poly-Si gate to suppress the boron penetration in pMOS , 1995, IEEE Electron Device Letters.

[72]  Chih-Yuan Lu,et al.  Recovery phenomenon and local field sensitivity on wafer charge-up effect of magnetically enhanced reactive ion etch system , 1995, IEEE Electron Device Letters.

[73]  Donggun Park,et al.  Reliability of thin SiO/sub 2/ at direct-tunneling voltages , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[74]  Hiroshi Iwai,et al.  Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[75]  Byung Jin Cho,et al.  Quasi-breakdown of ultrathin gate oxide under high field stress , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[76]  D. Wristers,et al.  Polarity dependence of dielectric breakdown in scaled SiO/sub 2/ , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[77]  K.P. Cheung.  An efficient method for plasma-charging damage measurement , 1994, IEEE Electron Device Letters.

[78]  J. McVittie,et al.  Modeling of oxide breakdown from gate charging during resist ashing , 1994 .

[79]  C. Hu,et al.  Effects of plasma charging damage on the noise performance of thin-oxide MOSFET's , 1994, IEEE Electron Device Letters.

[80]  B. S. Doyle,et al.  Effect of plasma-induced charging damage on n-channel and p-channel MOSFET hot carrier reliability , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[81]  Koji Eriguchi,et al.  Quantitative Evaluation of Gate Oxide Damage during Plasma Processing Using Antenna-Structure Capacitors , 1994 .

[82]  Suppression of boron penetration into an ultra-thin gate oxide (/spl les/7 nm) by using a stacked-amorphous-silicon (SAS) film , 1993, Proceedings of IEEE International Electron Devices Meeting.

[83]  C. Hu,et al.  Impact of plasma charging damage and diode protection on scaled thin oxide , 1993, Proceedings of IEEE International Electron Devices Meeting.

[84]  S. Salimian,et al.  Study of gate oxide damage in an electron cyclotron resonance argon plasma , 1992 .

[85]  Chenming Hu,et al.  Ultra-thin silicon dioxide leakage current and scaling limit , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[86]  J. McVittie,et al.  Thin-oxide damage from gate charging during plasma processing , 1992, IEEE Electron Device Letters.

[87]  R. Chau,et al.  Correlation of plasma process induced charging with Fowler-Nordheim stress in p- and n-channel transistors , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[88]  E. Cabruja,et al.  Characterization of the Electrical Damage due to Polysilicon RIE ( SF 6 + Cl2 Plasma ) Etching , 1992 .

[89]  M. Orlowski,et al.  Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from P/sup +/ gates , 1992, IEEE Electron Device Letters.

[90]  S.J. Wang,et al.  Effects of poly depletion on the estimate of thin dielectric lifetime , 1991, IEEE Electron Device Letters.

[91]  D. Buchanan,et al.  Vacuum ultraviolet radiation damage in electron cyclotron resonance and reactive ion etch plasmas , 1991 .

[92]  C. Gabriel.  Gate oxide damage from polysilicon etching , 1991 .

[93]  W. Greene,et al.  Magnetron etching of polysilicon: Electrical damage , 1991 .

[94]  C. Hu,et al.  Thin oxide charging current during plasma etching of aluminum , 1991, IEEE Electron Device Letters.

[95]  C. Lu,et al.  A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporation , 1990 .

[96]  James D. Hayden,et al.  The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices , 1990 .

[97]  A. Boudou,et al.  Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2>or=V/sub g/, 1990 .

[98]  M. Koyanagi,et al.  Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing , 1989 .

[99]  Yuan Taur,et al.  Study of boron penetration through thin oxide with p+-polysilicon gate , 1989 .

[100]  Y. Hokari,et al.  Stress voltage polarity dependence of thermally grown thin gate oxide wearout , 1988 .

[101]  J. Asmussen,et al.  Plasma etching with a microwave cavity plasma disk source , 1988 .

[102]  A. S. Grove,et al.  Redistribution of Acceptor and Donor Impurities during Thermal Oxidation of Silicon , 1964 .

[103]  L. Kevin,et al.  A Comprehensive Study on p + Polysilicon-Gate MOSFET ' S Instability with Fluorine Incorporation , 2022 .