An Improved Cellular Nonlinear Network Architecture for Binary and Grayscale Image Processing

Cellular nonlinear networks (CNNs) constitute a very powerful paradigm for single instruction/multiple data computers with fine granularity. Analog and mixed-signal implementations have proven to be suitable for applications in high-speed image processing, robot control, medical signal processing, and many more. Especially digital emulations on field-programmable gate arrays (FPGAs) allow the development of general-purpose computers based on the CNN universal machine with an inherently parallel structure, a high degree of flexibility and a superior computational precision. However, these emulations turn out to be inefficient for the execution of binary operations, which account for more than two-thirds of all processing steps in a typical CNN algorithm. In this contribution, we present an architecture for the emulation of CNNs that supports both a fast and efficient processing of binary images, and a high computational accuracy when needed. With the FPGA implementation of this architecture, a speed-up factor of up to 5 is achieved for binary-data operations.

[1]  Tamás Roska,et al.  The CNN universal machine: an analogic array computer , 1993 .

[2]  Leon O. Chua,et al.  Analogic CNN algorithms for some image compression and restoration tasks , 1995 .

[3]  Ricardo Carmona-Galán,et al.  A VLSI-oriented continuous-time CNN model , 1996, Int. J. Circuit Theory Appl..

[4]  Przemyslaw Mroszczyk,et al.  Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Vedat Tavsanoglu,et al.  Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  José Manuel Ferrández,et al.  A scalable CNN architecture and its application to short exposure stellar images processing on a HPRC , 2015, Neurocomputing.

[7]  Ákos Zarándy,et al.  Focal-Plane Sensor-Processor Chips , 2014 .

[8]  Victor M. Brea,et al.  SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems , 2012, 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors.

[9]  Ángel Rodríguez-Vázquez,et al.  A CMOS Vision System On-Chip with Multi-Core, Cellular Sensory-Processing Front-End , 2010 .

[10]  Ronald Tetzlaff,et al.  Hierarchical description and analysis of CNN algorithms , 2014, 2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA).

[11]  Ákos Zarándy,et al.  Configurable 3D-integrated focal-plane cellular sensor–processor array architecture , 2008 .

[12]  Fayaz Khan,et al.  A Cellular Network Architecture with Polynomial Weight Functions , 2018 .

[13]  Péter Szolgay,et al.  Configurable multilayer CNN-UM emulator on FPGA , 2003 .

[14]  Ronald Tetzlaff,et al.  NEROvideo: a general-purpose CNN-UM video processing system , 2014, Journal of Real-Time Image Processing.

[15]  Lin-Bao Yang,et al.  Cellular neural networks: theory , 1988 .

[16]  Ronald Tetzlaff,et al.  NERO mastering 300k CNN cells , 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

[17]  Ángel Rodríguez-Vázquez,et al.  ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.