论文信息 - A 36-bit balanced moduli MAC architecture

A 36-bit balanced moduli MAC architecture

Recently a renewed interest is seen in RNS (Residue Number System) which stems out from the fact that these systems are inherently parallel and modular and thus are fast and simple. In many DSP applications Multiply-Accumulate (MAC) operation turns out to be the most basic one and hence an RNS based 36-bit MAC architecture is presented in this paper to speed up the whole operation. A further enhancement in speed up is achieved by exploiting the logarithmic properties of Galois fields and integer rings. The choice of forward and reverse converters used in the design results in considerable savings in silicon real estate. The adder cells used is based on pass transistor design which attribute to very low power consumption.

A. P. Preethy | D. Radhakrishnan

[1] Gian Carlo Cardarilli,et al. Structurally passive digital filters in residue number systems , 1988 .

[2] M. Dugdale,et al. Residue multipliers using factored decomposition , 1994 .

[3] Jimson Mathew,et al. Using the 2 n Property to Implement an Efficient General Purpose Residue-to-Binary Converter , 2000 .

[4] D. Radhakrishnan,et al. Novel approaches to the design of VLSI RNS multipliers , 1992 .

[5] Michael A. Soderstrand,et al. Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[6] D. Radhakrishnan,et al. Modulo multipliers using polynomial rings , 1998 .

[7] Fred J. Taylor,et al. A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications , 1995, IEEE Trans. Computers.

[8] A. P. Preethy,et al. A novel 36 bit single fault tolerant multiplier using 5 bit moduli , 1998, Proceedings of IEEE TENCON '98. IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control (Cat. No.98CH36229).