Geometric approach to VLSI layout compaction

We present a new geometric approach to VLSI layout compaction in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass both compaction grids and constraint graphs during the entire compaction process. A systematic and efficient way is introduced to enumerate all possible jogs. For the given layout topology we prove that the geometric algorithm yields the minimum-area layout in one-dimensional compaction with automatic jog insertion. In the final output, only necessary jogs are inserted and the total wire length is minimized as a secondary goal. Furthermore, the integration of local compaction tools into a layout CAD system and the practical extensions of our algorithm are addressed.

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