Multiple-input neuron MOS operational amplifier for voltage-mode multivalued full adders

A CMOS operational amplifier employing the multiple-input-terminal transistor called neuron MOSFET (or /spl nu/MOS) as pair transistors has been developed. The circuit can perform a variety of analog voltage summation/subtraction operations in a very simple circuitry. The self-offset-cancellation capability has been implemented by a clocked /spl nu/MOS technique. As a result, high-accuracy voltage-mode signed-digit computation has become possible. The /spl nu/MOS operational amplifier has been applied to build a carry-propagation-free multivalued full adder circuit based on the radix-4 seven-valued signed-digit number system. The circuit operation has been verified by test circuits fabricated by Tohoku University standard double-polysilicon CMOS process with a 3 /spl mu/m rule.

[1]  Shoji Kawahito,et al.  A multiplier chip with multiple-valued bidirectional current-mode logic circuits , 1988, Computer.

[2]  Michitaka Kameyama,et al.  A 32 × 32 BIT multiplier using multiple-valued MOS current-mode circuits , 1987, 1987 Symposium on VLSI Circuits.

[3]  Tadashi Shibata,et al.  Neuron-MOS multiple-valued memory technology for intelligent data processing , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[4]  Ranjeet Alexis,et al.  A multilevel-cell 32 Mb flash memory , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[5]  Hiroshi Makino,et al.  A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[6]  Michitaka Kameyama,et al.  Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems , 1990 .

[7]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[8]  W. Pitts,et al.  A Logical Calculus of the Ideas Immanent in Nervous Activity (1943) , 2021, Ideas That Created the Future.

[9]  Kenneth C. Smith The Prospects for Multivalued Logic: A Technology and Applications View , 1981, IEEE Transactions on Computers.

[10]  Michitaka Kameyama,et al.  A 1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[11]  Tadashi Shibata,et al.  Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[12]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[13]  Michitaka Kameyama,et al.  Design and implementation of quaternary NMOS integrated circuits for pipelined image processing , 1987 .

[14]  Daniel Etiemble,et al.  Comparison of binary and multivalued ICs according to VLSI criteria , 1988, Computer.