Time-interleaved sample clock generator for ultrasound beamformer application

A sample clock generator (SCG) for application in a 32-channel ultrasound receiver beamformer is proposed. The RX beamformer samples the echo signals at delayed timings to align them in the time domain before summing them. The proposed SCG employs a dual counter and comparator scheme to generate delayed sampling clocks with 4.17 ns delay control resolution. The SCG is implemented using Verilog RTL code and the analog block of the beamformer was modeled with ideal sample and hold circuits. The beamformer was simulated using a mixed-signal simulator and the results verify the feasibility of the proposed scheme.

[1]  Ka Lok Man,et al.  Design for testability in nano-CMOS analog integrated circuits using a new design analog checker , 2011, 2011 International SoC Design Conference.

[2]  Gerard C. M. Meijer,et al.  A programmable analog delay line for Micro-beamforming in a transesophageal ultrasound probe , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[3]  Koji Inoue,et al.  Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming , 2003 .

[4]  K. Kirk Shung,et al.  Design of a 64 channel analog receive beamformer for high frequency linear arrays , 2010, 2010 IEEE International Ultrasonics Symposium.

[5]  J.F. Greenleaf,et al.  Ultrasonic dynamic focusing using an analog FIFO and asynchronous sampling , 1994, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[6]  Steven Guan,et al.  Design, analysis, tools and applications for programmable high-speed and power-aware 4G processors , 2011, 2011 International SoC Design Conference.