The Design of a High-Speed Image Acquisition System

Image acquisition system is responsible for collecting and filtering the image data to reduce the size of data processing. The efficiency of image acquisition will directly affect our ability to process image information timely and accurately. This paper proposes a hardware scheme for high-speed image acquisition system. The high performance of FPGA is fully taken to realize the logic control of this system. The principle, function and design methods of each sub-module have been described in detail.

[1]  Huijie Ji,et al.  Research on Image Median Filtering Algorithm and Its FPGA Implementation , 2009, 2009 WRI Global Congress on Intelligent Systems.

[2]  Sos S. Agaian,et al.  Efficient FPGA implementation of convolution , 2009, 2009 IEEE International Conference on Systems, Man and Cybernetics.

[3]  Tsutomu Maruyama,et al.  How fast is an FPGA in image processing? , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[4]  Donglai Xu,et al.  An FPGA-based low-cost frame grabber for image processing applications , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[5]  Thomas J. Olson,et al.  Programming a pipelined image processor , 1993, 1993 Computer Architectures for Machine Perception.

[6]  Wang Jun,et al.  Design of High frame frequency CMOS real-time image acquisition system , 2008 .