On overcoming the limitations of single-ended signaling for graphics memory interfaces

In this paper, we explore the effectiveness of various solutions that can be applied to improve the performance of SE signaling at small incremental cost to the system. Specifically, we examine solutions for mitigating the impact of crosstalk, supply noise, and inter-symbol interference (ISI) to enable reliable communication over a graphics memory channel at 12.8-Gbps. We further compare measured silicon data from a 12.8-Gbps SE interface to a 20Gbps differential (DIFF) interface, implemented in the same silicon technology and sharing many of the critical circuits.

[1]  Young-Hyun Jun,et al.  A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  S. Stille.  SPI Proceedings: Impact of Motherboard High Density Interconnect on High Speed Signaling , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

[3]  Timothy M. Hollis.  Data Bus Inversion in High-Speed Memory Applications , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Amir Amirkhany,et al.  Statistical simulation of SSO noise in multi-gigabit systems , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

[5]  A. Amirkhany,et al.  A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[6]  Ting Wu,et al.  A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface , 2009, IEEE Journal of Solid-State Circuits.

[7]  Young-Hyun Jun,et al.  A 0.13-$\mu$ m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN , 2009, IEEE Journal of Solid-State Circuits.

[8]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..