Cmos current comparator: Simplified analysis of the delay time

The maturity of current-mode analogue signal processing has led to the development of many systems based on the current-mode approach. ',' In particular, AID converter^^-^ seem to be very interesting on account of their speedy performance related to their dimensions. However, no papers have discussed the dynamic operation of the current comparator, which is the main building block of AID converters. In this letter the delay time of a CMOS current comparator' (see Figure 1) when we apply a step input to the circuit is analysed. For our purpose we define the delay time as the time required to reach an output voltage equal to 10 per cent of the maximum possible voltage. The work leads to a simple equation which can be helpful in a pencil-and-paper design procedure. Naturally, more accurate results can be obtained using a computer programme such as SPICE, which manages more complicated MOS transistor models.