On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC

With the high integration of integrated circuits, small delay faults have occurred as the cause of a circuit failure. We have proposed a method for testing small delay faults using a boundary scan circuit with embedded TDC (TDCBS). In this method, delay faults are detected by using the number of stages in which a transition signal has propagated through a delay line. However, there exists delay variation in a delay line. This paper investigated delay variation by measuring transition delay for different paths in the delay line. In addition, to calibrate delay variation, we investigated a calibration method for considering the variation of wire length and delay in a delay line in TDCBS. Measurement results for an experimental chip show that the method can compensate the variations in the delay line.

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