Abstract In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed VT/Vfb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the VT-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining VT-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.